Researchers propose self-organising digital circuits that reconfigure logic around faults with near-perfect accuracy

Researchers introduce Self-Organising Digital Circuits, a framework that treats functional logic generation and maintenance as a meta-learning problem on graphs, drawing inspiration from biological adaptive plasticity rather than classical static fault-tolerance strategies like hardware redundancy or error-correcting codes.

The proposed architecture uses a topology-masked Transformer to configure the lookup tables of a circuit's Boolean gates, extending the pattern-generation paradigm of Neural Cellular Automata to navigate the degenerate Boolean search space and satisfy a computational task rather than regenerating a fixed target state.

The authors demonstrate that the system can self-assemble functional circuits from scratch and rapidly re-route logic around permanent, previously unseen hardware faults, indicating robustness to novel damage scenarios.

For soft errors, the policy achieves near-perfect recovery with greater than 99.99% accuracy even when the damage size exceeds conditions seen during training, suggesting strong resilience beyond the training distribution.

The work further reports generalisation across circuit scales, with accuracy improving on graphs substantially wider than those encountered during training, highlighting potential scalability to larger or more complex hardware designs.